1. Field of the Invention
The present invention relates to the field of testing integrated circuits having logic circuits testable by on chip scan chains; more specifically, it relates to a method of diagnosing stuck-at fails of the scan chains.
2. Related Documents
This application is related to U.S. Pat. No. 6,442,723 to Koprowski et al., which is hereby incorporated by reference in its entirety.
3. Background of the Invention
Complex very large-scale integrated circuits contain very large numbers of logic circuits that require extensive testing. In order to mitigate the complexity of the testing required, scan based designs have been implemented. However, a problem with scan-based designs has been diagnosing fails, notably stuck-at one or stuck-at zero, of individual shift register latches (SRL) in the SRL chains. The difficulty of distinguishing with certainty fail signatures caused by failure of the logic circuits from fail signatures caused by stuck-at failure of individual SRLs in the SRL chains inhibits rapid determination of the root cause of the fail and can delay corrective action.